Bonded wires, solder bumps and metal pillars are common microstructures formed on micro devices which are usually fabricated on silicon wafers. Wire bonding is the earliest technique for interconnecting electronic devices. Thermosonic wire bonding is a commonly used technique. Conventional wire bonding allows Input/Output (I/O) pad bonding only on a chip perimeter near edges of a chip. Low profile and flexible long loop wire can be bonded across multiple chips and substrates. However, the trade-off in long wire interconnection is its high impedance and parasitic inductance and capacitance. Wire bonding is usually not suitable for high frequency and RF applications. Further, wire bonding over an active portion of a silicon chip may damage the delicate circuitry beneath it. This restriction limits the design for optimal power distribution and chip size shrinkage.
Flip-chip technology is an important development for the microelectronic industry. An optimized flip-chip device provides improvement in cost, reliability and performance over a wire-bonded device. The flip-chip device also has better electrical performance and lower impedance, inductance and capacitance. Aided by a self-alignment characteristic of solder, flip-chip packaging using solder bump has excellent yield. An area array interconnection format on flip-chip allows large number of I/Os to be distributed across the chip surface. This improves pitch spacing and power distribution. With no additional packaging material over the bare chip, the flip-chip has the smallest possible size. As the flip-chip array pitch decreases, the interconnect solder bump diameter on the flip-chip may decrease correspondingly.
One disadvantage for reducing a solder bump size is the increase in the volume ratio of the IMC to bulk solder in an interconnecting joint. A higher percentage of the IMC in the solder joint is undesirable as the IMC is brittle and the fatigue life of the solder joint can be reduced. Another disadvantage is the increase in current density as the solder bump size decreases. As current density increases, electromigration will become a reliability concern in package interconnection.
FIG. 1 shows a schematic drawing of a typical solder bump interconnection 100. The typical solder bump interconnection 100 comprises an under-bump-metallization (UBM) 102, a solder bump 104 and a matching substrate bond pad 106. However, the typical solder bump interconnection 100 has several inherent weaknesses. During reflow, the solder bump 104 will collapse and become barrel-shaped upon solidification. This limits the height and pitch of solder joints and applications of the solder bump interconnection 100 in high-density miniaturized packages. Further, truncated spherical ends 108 of the solder bump 104 are the main load bearing points and high stress concentrations occur at these spherical ends 108. UBM 102 interacts with the solder bump 104 and weakens the solder joints. Embrittlement at the IMC-solder interfaces 110 and coefficient of thermal expansion (CTE) mismatch in these IMC-solder interfaces 110 creates node for crack initiation and propagation.
Unlike solder bump, copper (Cu) pillar does not collapse during reflow soldering. Pillars can be packed closer together, increasing the interconnection density. If plating is done directly on the chip metal pads, intermetallic compound (IMC) formation on the chip interface is avoided. The concern of solder diffusion and interaction with the thin films on the chip is also eliminated. In addition, failure is unlikely to happen on the chip interface since Cu mechanical properties are much better than solder. The pillar structure can also be engineered such that stress concentration and shear strain on solder is reduced.
FIGS. 2a and 2b show a schematic drawing of a conventional pillar interconnect design 200 with a larger and a smaller pillar diameter respectively. A key issue of the conventional pillar interconnect design 200 is that the solder volume 204 and its wetting surface 206 vary as the diameter of the pillar 202 changes. The pillar 202 with a smaller diameter, as shown in FIG. 2b, increases compliance as compared to the pillar 202 with a larger diameter, as shown in FIG. 2a. However, the wetting surface 206 decreases when the diameter of the pillar 202 becomes smaller. A decrease in the wetting surface 206 may affect joint reliability. In addition, solder bumping cannot be done on a device with varying pillar diameters as this will result in non-planarity.
Hence, there is a need to provide an alternative interconnect structure, and method which seek to address at least one of the above-mentioned problems.